Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

SEMATECH has sponsored a " Test Method Evaluation " study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including " IDDq-only " failures and " delay test-only " failures. 1.0 Introduction In order to optimize future testing methods, it is important to understand as much as possible about existing failure mechanisms -i.e., defect types, defect behavior, changes in defect behavior over time (stressing) and the effectiveness of various tests to detect these defects. Historically, detailed and comprehensive defect data has not been published-mainly because of company confidential information concerns. Also, information about defect types that are undetected with existing manufacturing tests (i.e., the defect types that should be targeted with improved test methods) is often not known by manufacturers because of the difficulty in detecting and characterizing " undetected " defect types. In particular, there is little manufacturing data published about the probability and behavior of defect types such as " timing-only defects " , " IDDq-only defects " , and " stuck-open defects ". There are some key, defect-related issues for the industry in general for which there are apparently little consensus or published data based on large sample sizes, e.g., • Should all ICs with abnormal IDDq be scrapped-even those passing all other tests ? • Are IDDq-only failures caused by unique defect mechanisms ? • Will the defect mechanisms causing timing-only failures become more problematic with advanced technologies ? • What defect mechanisms currently escape " reasonably complete " stuck-fault tests in addition to timing or IDDq failures ? • Are existing diagnostic and failure analysis tools sufficient ? Are existing fault models sufficient for diagnostics ? The lack of such defect characterization information severely limits the effectiveness of researchers looking at test method improvements. Although inductive fault analysis [3, 4] is a very useful defect simulation tool, it alone is not sufficient to understand all defect types, behaviors and probabilities. Hardware-based defect characterization is needed. Without complete defect information, test methodology trade-offs and product quality estimates are often based upon overly simplistic or incorrect assumptions. In this paper, we will summarize the failure analysis portion of a test-related study sponsored by SEMATECH. In particular , we will describe the results of …